An ESD event refers to a phenomenon of electrical discharge of a current (positive or negative) for a short duration during which a large amount of current is provided to an integrated circuit (IC). The large current may be built-up from a variety of sources, such as the human body. An ESD event commonly results from the discharge of a high voltage potential (typically, several kilovolts) and leads to pulses of high current (several amperes) of a short duration (typically, 100 nanoseconds). An ESD event is generated within an IC, illustratively, by human contact with the leads of the IC or by electrically charged machinery being discharged in other leads of an IC. During installation of integrated circuits into products, these electrostatic discharges may destroy the IC and thus require expensive repairs on the products, which could have been avoided by providing a mechanism for dissipation of the electrostatic discharge to which the IC may have been subjected.
Manufacturers and users of ICs must take precautions to avoid ESD. For example, ESD prevention can be part of the device itself and may include special design techniques for device input and output pins. Additionally, external protection components can also be used with the circuit layout. For example, to protect ICs from an ESD event, many schemes have been implemented for ESD structures, including, for example, the use of a silicon controlled rectifier (SCR). An SCR can sustain high currents, hold the voltage across the SCR at a low level and may be implemented to bypass high current discharges associated with an ESD event.
ESD devices may also be used to prevent latchup and provide noise isolation. More specifically, noise isolation and the elimination of complementary metal-oxide semiconductor (CMOS) latchup are significant issues in advanced CMOS technology, radio frequency (RF) CMOS, and bipolar CMOS (BiCMOS) Silicon Germanium (SiGe) technology. Latchup conditions typically occur within peripheral circuits or internal circuits, within one circuit (intra-circuit), or between multiple circuits (inter-circuit). In one such example, latchup occurs when a PNPN structure transitions from a low-current/high-voltage state to a high-current/low-voltage state through a negative resistance region (i.e., forming an S-Type I-V (current/voltage) characteristic).
Latchup can occur as a result of the interaction of an electrostatic discharge (ESD) device, the input/output (I/O) off-chip driver and adjacent circuitry initiated in the substrate from the overshoot and undershoot phenomena. These factors can be generated by CMOS off-chip driver (OCD) circuitry, receiver networks, and ESD devices. In CMOS I/O circuitry, undershoot and overshoot can lead to injection in the substrate, and simultaneous switching of circuitry where overshoot or undershoot injection occurs may lead to both noise injection and latchup conditions. Also, supporting elements in these circuits, such as pass transistors, resistor elements, test functions, over voltage dielectric limiting circuitry, bleed resistors, keeper networks and other elements can be present, contributing to noise injection into the substrate and latchup.
Latchup also can occur from voltage or current pulses that occur on the power supply lines. For example, transient pulses on power rails (e.g., substrate or wells) can trigger latchup processes. Latchup can also occur from a stimulus to the well or substrate external to the region of a thyristor structure from minority carriers.
Additionally, latchup can be initiated from internal or external stimulus, and is known to occur from single event upsets (SEU), which can include terrestrial emissions from nuclear processes, and cosmic ray events, as well as events in space environments. Cosmic ray particles can include proton, neutron, and gamma events, as well as a number of particles that enter the earth atmosphere. Terrestrial emissions from radioactive events, such as alpha particles, and other radioactive decay emissions can also lead to latchup in semiconductors.
In operation, ESD structures (or networks) require low resistance current paths to discharge high currents to the VDD (positive) power supply and the VSS (negative) power supply. That is, ESD networks need a low resistance shunt to the substrate. Additionally, ESD circuits are needed that contain both active elements and passive elements. Furthermore, ESD elements use guard rings to isolate minority carrier injection to adjacent structures.
An aim of ESD circuits is to provide a low resistance path to a substrate. Conventionally, standard metal levels are used to provide this low resistance path. However, as the metal levels are getting thinner due to scaling, the wiring levels provide greater capacitance between the different physical levels.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.